Phase margin vs damping factor?

Same property, different domains. Rough Type-2 mapping: PM 30° ≈ ζ 0.3 (underdamped); PM 45° ≈ ζ 0.5; PM 60° ≈ ζ 0.8 (well damped); PM 70°+ ≈ ζ 1+ (overdamped slow settling).

Does this tool model the sampled-time loop?

No — continuous-time linear approximation only (industry standard for initial design). Excellent for BW « fref/10. For very wide loops follow up with Z-domain or behavioural simulation. Tool flags BW > fref/10.

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Phase-Frequency Detector (PFD) Simulator

Visualize PFD timing in a charge-pump PLL — REF vs FB, UP/DN pulses, and average charge-pump current — then design the Type-2 loop filter (R, C, optional 3rd-order pole) for a given bandwidth and phase margin, with the resulting open-loop Bode plot.

Inputs

Reference frequency 10 MHz

Phase error (REF − FB) 0°

PFD's linear range is ±360° (±2π). Beyond that it slips a cycle.

Charge-pump current 1 mA

Result

Phase error

—

φ = REF phase − FB phase

UP pulse width

—

REF leads → UP high

DN pulse width

—

FB leads → DN high

Average charge-pump current

—

I_avg = I_cp · φ / (2π)

LOCKED

PFD output rule

UP/DN pulse width = |φ| / (2π · f_ref)

Timing — REF, FB, UP, DN over 3 reference cycles

Loop specifications

Preset

Reference frequency 25 MHz

Used for spur / sampling-limit checks. BW < f_ref/10 is the conventional safe limit.

Divider N 100

VCO gain K_vco 100 MHz/V

Charge-pump current I_cp 1 mA

Loop bandwidth BW 50 kHz

Phase margin 50°

Filter order

C : C_p ratio 1:10

Only used in 3rd-order mode. Typical 10:1 puts the extra pole ≈ 10× above BW.

Component values

C (main)

—

C = I_cp·K_vco / (cos PM · N · ω_c²)

R (zero)

—

R = sin PM · N · ω_c / (I_cp·K_vco)

C_p (3rd-order pole)

—

C_p = C / k

RC zero time constant

—

τ_z = R·C = tan(PM)/ω_c

Crossover f_c

—

where |T(jω)| = 1

Achieved phase margin

—

180° + ∠T(jω_c)

Stable design

Open-loop transfer function

T(s) = I_cp·K_vco · (1 + sRC) / (s² · N · C · (1 + sRτ₃))

Open-loop magnitude — |T(jω)| in dB vs frequency

Open-loop phase — ∠T(jω) in degrees vs frequency

PFDs, Charge Pumps & PLL Loop Filters

A phase-frequency detector (PFD) is the front end of nearly every modern phase-locked loop. Compared to a simple XOR or mixer-style phase detector, the PFD has two huge advantages: a linear range of one full cycle (±2π rad), and an output that's sensitive to frequency difference as well as phase difference. The second property is what lets a PLL acquire lock from any starting frequency offset.

How the PFD works

The classic three-state PFD is two D flip-flops with their D inputs tied high. REF clocks one, FB (the divided VCO) clocks the other. The Q outputs are UP and DN. An AND gate resets both flip-flops whenever both go high simultaneously. The behaviour:

REF leads FB by Δt: UP goes high on REF's rising edge, stays high until FB's rising edge resets both. UP pulse width = Δt; DN pulse ≈ 0 (just the reset-path delay).
FB leads REF by Δt: DN goes high on FB's rising edge, resets when REF arrives. DN pulse width = Δt; UP ≈ 0.
Perfect lock: UP and DN go high together briefly each cycle (matched edges → reset). The "deadband" is just the reset-path propagation delay (~1 ns) — vanishingly small ripple.
Frequency error: faster input keeps triggering its flip-flop while the slower one hasn't caught up. The PFD spends almost all of its time pulling the loop in the right direction. This is what gives charge-pump PLLs their "infinite" capture range.

The charge pump

UP and DN drive a charge pump — typically a pair of matched current sources/sinks. When UP is high, +I_cp flows into the loop filter; when DN is high, −I_cp flows out. The average current per reference cycle is I_avg = I_cp · φ / (2π) where φ is the phase error in radians. The combined PFD+CP block is therefore a perfectly linear phase-to-current converter with gain K_pd = I_cp / (2π) A/rad.

Type-2 loop filter — the standard choice

The charge pump's output is a current; you need a filter that converts that to a control voltage for the VCO. The simplest stable design is a Type-2 lead-lag: a capacitor C in series with a resistor R, with the VCO control voltage taken across the C. The filter impedance is Z(s) = R + 1/(sC) — an integrator (the 1/sC term) plus a stabilising zero (the R term) at ω_z = 1/(RC). The integrator gives infinite DC gain (so static phase error → 0); the zero provides phase margin for stability.

Designing for a chosen bandwidth and phase margin

Once you pick a target loop bandwidth ω_c (the unity-gain crossover) and a phase margin PM, the component values fall out as:

R·C = tan(PM) / ω_c — sets the zero location to give the desired phase margin
C = I_cp·K_vco / (cos(PM) · N · ω_c²) — sets the open-loop magnitude to 1 at ω_c
R = sin(PM) · N · ω_c / (I_cp·K_vco) — solve the above two together

This gives you exactly 1 at ω_c with exactly PM phase margin. Adding a 3rd-order pole (an extra cap C_p = C/10 in parallel) attenuates reference spurs at multiples of f_ref, but slightly reduces the actual phase margin — the tool shows you the achieved PM with C_p included.

The "bandwidth < f_ref/10" rule

The CP-PLL is fundamentally a sampled-data system; the PFD samples once per reference cycle. The continuous-time linear analysis above only holds when the loop bandwidth is well below the sampling rate, conventionally BW < f_ref/10. Push past that and the loop will exhibit instability and excess ripple not predicted by Bode analysis. The tool flags this in the stability badge.

Frequently Asked Questions

Why does the UP or DN pulse width go to zero at exact lock?

Because at perfectly aligned edges, the AND-gate reset fires the instant both flip-flops go high. The "pulse" still exists but it's only as long as the reset propagation delay (~1 ns), which dumps a negligible amount of charge into the loop filter. This near-deadband behaviour gives charge-pump PLLs their excellent reference-spur performance compared to XOR-detector PLLs.

What's the difference between phase margin and damping factor?

They describe the same stability property in different domains. Phase margin (frequency domain) is what's left of the 180° before the open-loop gain reaches unity. Damping factor ζ (time domain) governs how the closed-loop step response decays. For Type-2 PLLs the rough mapping is: PM 30° ≈ ζ 0.3 (very underdamped, lots of ring); PM 45° ≈ ζ 0.5 (some overshoot); PM 60° ≈ ζ 0.8 (well damped); PM 70°+ ≈ ζ 1+ (overdamped, slow settling).

Why does my computed C come out impossibly large?

Because the design constraints are physically inconsistent. C scales as I_cp·K_vco / (N · ω_c²). For very low BW (small ω_c) with a normal Kvco and Icp, C balloons into farads. Fix: reduce Kvco (use a less sensitive VCO), reduce Icp (1 µA chargepumps exist), or accept a higher BW. The stability badge warns when C > 1 mF — at that point you should reconsider the spec, not buy a 47 mF film capacitor.

Should I pick 2nd-order or 3rd-order?

2nd-order (just R and C) is mathematically cleanest and gives exact phase margin. 3rd-order adds a small cap C_p in parallel for extra rolloff above the bandwidth, which is mainly there to suppress reference-frequency spurs in fractional-N synthesizers. Cost: it eats a few degrees of phase margin. For wideband loops or where spur suppression isn't critical, 2nd-order is fine. For frequency synthesizers (the typical use case), 3rd-order is standard.

What phase margin should I target?

For most CPPLLs, 50° is the textbook starting point — gives reasonable damping (ζ ≈ 0.6) and fast settling. 45° is the absolute minimum for stable operation; below 40° the loop will ring badly on any transient. 60° is conservative — slower settling but very low overshoot, common in clock-recovery PLLs where jitter matters more than acquisition speed. Above 65° starts to lose lock-time performance with diminishing stability benefit.

Why is the linear range exactly ±2π and not ±π?

The three-state PFD only resets when both flip-flops go high; until then the leading input keeps producing pulses on its side. So between -2π and +2π (one full FB cycle of misalignment), the average output is monotonically linear with phase. Beyond ±2π, the PFD "slips" — the trailing input misses a cycle entirely and the average output saturates rather than wrapping. A simple XOR detector, by contrast, is sinusoidal in phase and only linear over ±π/2.

How do I size the charge-pump current?

Pick I_cp so the resulting C falls in a buildable range (1 nF – 1 µF roughly). Larger I_cp makes the loop faster for a given BW but increases reference spurs (more charge per pulse → more ripple). Typical CPPLL chips offer 100 µA – 5 mA programmable; if your tool gives huge C, raise I_cp; if it gives tiny R (< 10 Ω), lower I_cp.

Does this tool model the discrete-time (sampled) loop?

No — only the continuous-time linear approximation, which is industry standard for initial design. For BW well below f_ref/10 the approximation is excellent. For very wide loops near f_ref/10 you should follow up with a Z-domain or behavioural simulation (e.g. Cadence ADE or open-source Discrete-Time PLL toolbox in Python). The tool flags BW > f_ref/10 in the stability badge.

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